/designs · open chip design library
Open Chip Design Library
Each entry is a downloadable Build Package — manifest, layout, BOM, test plan, calibration plan, reliability plan, and a pre-filled RFQ template. Every design has a manufacturing pathway status, not just a star count.
Maturity status taxonomy
ConceptSimulatedTapeout-readyMPW-testedPackage-compatibleCalibration-readyModule-readyQualified
Concept → Simulated → Tapeout-ready → MPW-tested → Package-compatible → Calibration-ready → Module-ready → Qualified. Status reflects the furthest-verified state of a design's manufacturing pathway.
DesignNodePackagesLicensePackage
- esc-4x4-tile-v0.1ESC 4×4 TileMixed-signal sensor front-end tile with CAN, SPI, and analog BIST. Reference design for robotics and rugged industrial control.MPW-tested180nmQFN-64QFP-100BGA-121CERN-OHL-S v2↓ ZIP · 9.8 KB
- can-lin-interface-v0.2CAN / LIN Fault-Tolerant InterfaceAutomotive-grade transceiver pair with on-die ESD pulse protection. Drop-in for legacy ECU upgrades.Tapeout-ready130nmQFN-32QFP-48Solderpad 2.1↓ ZIP · 9.5 KB
- industrial-sensor-asic-v0.1Industrial Temp + Vibration Sensor ASICLow-power predictive-maintenance sensor with integrated DSP, calibration store, and I²C/SPI host interfaces.Simulated65nmQFN-40WLCSP-25Apache 2.0↓ ZIP · 10.3 KB
Submit a design
Have an open-source design that fits this portal's mature-node + module-ready remit?
v0 of MOMF accepts submissions by email — attach a draft DESIGN_MANIFEST.yaml and a process/package target. Submissions are reviewed against the maturity-status taxonomy before being added to the public library.
Email a submission →